Electrostatic discharge (“ESD”) is the principal cause of damage to integrated circuits. Presently, semiconductor circuits, such as, for example, CMOS amplifiers and digital circuits, often utilize on-chip ESD protection devices comprising of diodes added to the circuit. Typically, these protection circuits comprise diodes added in a back to back configuration, which divert the charge away from vulnerable circuit nodes, such as, for example, signal inputs to the CMOS gates.
This conventional method of providing ESD protection can be theoretically ported to large signal circuits. In particular, such ESD protection schemes may be used to protect the gate of a metal oxide semiconductor field-effect transistor (“RF MOSFET”) power amplifier in a RF application. In such a scheme, back to back diodes are connected between the gate node and the Vdd and Vgg (i.e., GND) nodes of the MOS transistors. The drain and source nodes of the transistors themselves are generally connected to the voltage rail nodes as well. Thus, for each transistor, one diode is connected on-chip between the gate and drain of the MOS device that it is protecting, while a second diode is connected on-chip between the gate and the source of the same MOS device. The Vdd/Vgg nodes of the MOS and the ESD devices are thus connected on chip.
When electrostatic charge appears with respect to the drain or the source, the two diodes conduct in the forward/reverse mode depending on the polarity of the electrostatic charge, thereby diverting it away from the MOS gates.
As an added protective measure, a resistive feed can also be used for biasing the input gates of the MOS device. Such a resistor provides additional protection against ESD by dropping voltage across the resistor.
However, using these conventional techniques, the diodes will have a parasitic capacitive loading effect at the MOS gate and, possibly, the drain/source nodes, resulting in RF performance degradation of the amplifier. For small signal amplifiers, this added parasitic capacitance will be a constant, non temporally variant load. While such constant load does result in performance degradation, it does not introduce any non-linearity. Therefore, the added parasitic capacitance may be tolerable for small signal applications.
In the case of large signal power amplifiers however, significant voltage swings at the drain (for n-MOS transistors) can occur, going from zero to twice the amplifier's supply voltage, i.e., from zero to 2*Vdd. This is due to the nature of the inductive feed to the drain of the amplifying transistor. Simultaneously, the gate voltage can swing out of phase with the drain waveform. If this constellation of events occurs, in the worst case scenario the drain node can have a large negative voltage and the gate node its peak positive voltage. In such eventuality the diode across the gate and drain would be forward biased, resulting in the clipping of the gate voltage to the forward drop of the diode and cause distortion in the power amplifier. Even if the voltage swings do not occur, the reverse bias of the two diodes will change drastically with time. Consequently, the parasitic capacitance load will change non-linearly, introducing significant distortion in the power amplifier. As a result, the conventional ESD protection configuration cannot be justified for power amplifier circuits.
What is needed therefore is a power amplifier circuit with ESD protection that does not introduce additional parasitic capacitance.
It is an object of the present invention to present a method of ESD protection that minimizes or obviates the introduction of additional parasitic capacitance.
It is a further object of the present invention to provide a power amplifier circuit that incorporates an ESD protection device while minimizing or avoiding additional parasitic capacitive loading.